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RISC-V 
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Ранг: Форумен бог
Ранг: Форумен бог

Регистриран на: Вто Ное 06, 2018 4:18 pm
Мнения: 1312
Мнение Re: RISC-V
Ето тук се вижда резултата от симулацията
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Чет Апр 20, 2023 9:58 pm
Профил
Ранг: Форумен бог
Ранг: Форумен бог

Регистриран на: Вто Ное 06, 2018 4:18 pm
Мнения: 1312
Мнение Re: RISC-V
Ако искаме да пробваме друга програма отиваме ето тук: https://riscvasm.lucasteske.dev
След това си вкарваме асемблера и натискаме бутона BUILD. След това копираме генерирания машинен код от прозореца hex dump в кода на процесора, най отгоре. След това се прекомпилира и симулира с трите реда команди на gHDL, Изходният файл се отваря наново с GTKWave за да се види резултата от изпълнението на програмата.


Чет Апр 20, 2023 10:04 pm
Профил
Ранг: Форумен бог
Ранг: Форумен бог

Регистриран на: Вто Ное 06, 2018 4:18 pm
Мнения: 1312
Мнение Re: RISC-V
Малко ъпдейт на кода, направих няколко корекции - първата е че прехвърлих фърмуеъра в тест бенча и процесора си чете инструкциите през външна шина. Предимството е че при компилиране се синтезират всички инструкции докато преди това компилатора анализираше инструкциите в кода и компилираше само частта, която е заета с изпълнението на наличните, така нямах идея колко от ресурсите на FPGA-то ще заеме целия процесор. Сега обаче нямам възможност да тествам процесора на физическо устройство, мога само да го симулирам, ще го преправя пак когато се наложи да го тествам на платката.
Втората корекция е в ниво 2 на pipeline-а, в ALU-то, понеже изполвам канализация на 3 нива (3 stage pipeline), не знам термина на българси, в някои случаи процесора се налагаше да изчаква изпълнението на текущата инструкция, преди да продължи със следващата, това се нарича stalling - задържане. Примерно ако имаме две последователни инструкции - първата записва в регистър X3, а следващата чете от Х3 и извършва операция със стойността. Понеже процесора записва в регистъра по време на 3-то ниво на канала, то прочетената стойност на първо ниво няма да е актуална, затова процесора задържа първо ниво 3 такта преди да продължи за да прочете обновената стойност в регистъра Х3 - толкова е необходимо да изпълни ниво 3, РАМ-а да се обнови и да се прочете новата стойност на ниво 1. Такава архитектура е много проста но не е ефективна, за да се оптимизира вместо да се изчаква запис в паметта изходът от АЛУ-то се подава директо на входа при следващата инструкция, така няма задържане. Тук обаче нещата са много по-сложни отколкото изглеждат защото този проблем го има не само при две последователни инструкции запис/четене, но също така и при две инструкции запис-четене разделени с трета инструкция (несъседни). При втория случай трябва да съхраня изхода на АЛУ-то и да проверявам всяка следваща инструкция дали чете от мястото, където предходната инструкция записва. За капак задържането не може да се избегне изцяло, примерно при инструкцията jump процесора зарежда новия адрес на данновата шина но в тръбата има една инструкция, която се е заредила след инструкцията jump и коато трябва да се прескочи. В тоя случай се прави flushing - инструкцията jump се задържа 2 такта докато излишната инструкция се избута през канала без да се изпълнява. По-долу е новия код и новия тест бенч.

Код:
-- Create Date:    09:33:24 18/10/2022
-- Design Name:
-- Module Name:    RISC_V_Core - Behavioral
-- Project Name:   RISC_V
-- Target Devices: Efinix Trion T8F81
-- Tool versions:  Efinity 2022.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created               23/11/2022
-- Revision 0.1  - Initial version completed   9/12/2022
-- Revision 0.11 - Initial version tested     12/12/2022
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--
--
entity RISC_V_Core is
    Port ( RST               : in    std_logic;                       -- Reset signal
          PORT_A_in         : in    std_logic_vector(7 downto 0);    -- port declaration of bidirectional data line
         PORT_B_out        : out   std_logic_vector(7 downto 0);    -- port declaration of bidirectional data line
           CLK               : in    std_logic;                       -- Clock signal
         ADDRESS_BUS       : out   std_logic_vector(31 downto 0);   -- port declaration of bidirectional data line
         DATA_BUS          : in    std_logic_vector(31 downto 0)    -- port declaration of bidirectional data line
     );
end RISC_V_Core;
--
--
architecture Behavioral of RISC_V_Core is
--
     -- Enumerated operation
     type RISC_V_OPERATION is
     (o_SUM, o_SUB, o_SHIFT_LEFT, o_SHIFT_RIGHT, o_SRA, o_AND, o_OR, o_XOR, o_SLT, o_SLTU, o_LOAD, o_SAVE,
      o_BNE, o_BEQ, o_BLT, o_BGE, o_BLTU, o_BGEU, o_ILLEGAL);
     type DATA_F is
     (l_32, l_16, l_8, l_16_U, l_8_U);
--
     type X_REG is array (0 to 31) of signed(31 downto 0);
  --    type X_REG_1 is array (0 to 31) of signed(31 downto 0);
     type RAM_MEM is array (0 to 1023) of std_logic_vector(31 downto 0);
--
     signal   OPERATION             : RISC_V_OPERATION;
     signal   USER_MEM              : RAM_MEM;
      signal   X_REGISTER            : X_REG :=(                                           -- This array is identical to X_REGISTER_MIRROR and holds the STORE_REGISTERs
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000");
     signal   X_REGISTER_MIRROR     : X_REG :=(                                           -- This array is identical to X_REGISTER and holds the STORE_REGISTERs
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000");
     signal   DATA_FORMAT           : DATA_F;                                            -- Integer format for loading
     signal   DATA_FORMAT_2         : DATA_F;                                            -- Integer format for loading passed to Stage 3
      signal   PC                    : signed(31 downto 0)            := to_signed(0,32); -- PC Register
     signal   ARGUMENT1             : signed(31 downto 0)            := to_signed(0,32); -- Argument 1 for operation    
      signal   ARGUMENT2             : signed(31 downto 0)            := to_signed(0,32); -- Argument 2 for operation   
     signal   ARGUMENT3             : signed(31 downto 0)            := to_signed(0,32); -- Argument 3 for operation
     signal   SHIFT_STEPS           : integer range 0 to 31          := 0;               -- Shift Steps    
     signal   INSTRUCTION           : std_logic_vector(31 downto 0)  := X"00000000";     -- Instruction holding Register
     signal   DESTINATION           : std_logic_vector(4 downto 0)   := "00000";         -- Instruction holding Register
     signal   ARBIT                 : std_logic_vector(2 downto 0)   := "000";           -- ALU Input selecton index based on bypass conditions
     signal   STORE_REGISTER        : std_logic_vector(4 downto 0)   := "00000";         -- General Purpose Register Index
     signal   STORE_REGISTER_2      : std_logic_vector(4 downto 0)   := "00000";         -- General Purpose Register Index
     signal   U_REG                 : std_logic_vector(31 downto 0)  := X"00000000";     -- Formated U Type Immediate Register
     signal   SOURCE_REGISTER_1     : std_logic_vector(4 downto 0)   := "00000";         -- Source Register 1 extracted from the instruction
     signal   SOURCE_REGISTER_2     : std_logic_vector(4 downto 0)   := "00000";         -- Source Register 2 extracted from the instruction
     signal   SOURCE_REG_1_STAGED   : std_logic_vector(4 downto 0)   := "00000";         -- Source Register 1 after Pipeline Stage 2
     signal   SOURCE_REG_2_STAGED   : std_logic_vector(4 downto 0)   := "00000";         -- Source Register 2 after Pipeline Stage 2
      signal   RESULT                : signed(31 downto 0)            := to_signed(0,32); -- Result after the instruction execution
     signal   POST_RESULT           : signed(31 downto 0)            := to_signed(0,32); -- Result (copy) after Stage 3 - Store into Memory/Register
     signal   PORTA                 : signed(7 downto 0)             := to_signed(0,8);  -- PORT A buffer
     signal   STAGE_ENABLE          : std_logic_vector(2 downto 0)   := "000";           -- Bits for enabling the Pipeline Stages
     signal   J_PP                  : std_logic                      := '0';             -- JALR post processing flag
     signal   PC_WRITE              : std_logic                      := '0';             -- PC write flag for Stage 3
     signal   MEM_STORE             : std_logic                      := '0';             -- Register or Memory store flag for Stage 3
     signal   PC_WRITE_2            : std_logic                      := '0';             -- PC write flag for Stage 3
     signal   REG_STORE_2           : std_logic                      := '0';             -- Register or Memory store flag for Stage 3
     signal   LOAD_OP               : std_logic                      := '0';             -- Load instrunction flag for post-processing
     signal   sys_RES               : std_logic                      := '0';             -- Sincronously asserted system Reset
     signal   sinc_T1               : std_logic                      := '0';             -- Sinchronous Clock 1
     signal   sinc_T2               : std_logic                      := '0';             -- Sinchronous Clock 2
     signal   sinc_T3               : std_logic                      := '0';             -- Sinchronous Clock 3
     signal   RS1_REG               : std_logic                      := '0';             -- Register flag for SOURCE_REGISTER_1
     signal   RS2_REG               : std_logic                      := '0';             -- Register flag for SOURCE_REGISTER_2
     signal   RS1_REG_ST3           : std_logic                      := '0';             -- Register flag for SOURCE_REGISTER_1 in STAGE 3
     signal   RS2_REG_ST3           : std_logic                      := '0';             -- Register flag for SOURCE_REGISTER_1 in STAGE 3
     signal   RS1_REG_ST4           : std_logic                      := '0';             -- Register flag for SOURCE_REGISTER_1 in STAGE 3+1
     signal   RS2_REG_ST4           : std_logic                      := '0';             -- Register flag for SOURCE_REGISTER_1 in STAGE 3+1
     signal   ST2_HOLD              : std_logic                      := '0';             -- Flag for stalling, especially when reloading PC
     signal   ST3_HOLD              : std_logic                      := '0';             -- Flag for stalling, especially when reloading PC
     signal   OP_ADDRESS            : signed(31 downto 0)            := to_signed(0,32); -- LOAD ADDRESS
     signal   JAL_FLG               : std_logic                      := '0';             -- flag for JAL instruction
     signal   RS1_LINK              : std_logic                      := '0';             -- flag for source 1 -> destination match
--
      function SIGN_EXTENDED_I(a: in STD_LOGIC_VECTOR ) return STD_LOGIC_VECTOR is
        begin
         if (a(31) = '1') then return( "111111111111111111111" & a(30 downto 20));
        else return( "000000000000000000000" & a(30 downto 20));
        end if;
        end function SIGN_EXTENDED_I;
--
      function SIGN_EXTENDED_J(a: in STD_LOGIC_VECTOR ) return STD_LOGIC_VECTOR is
        begin
         if (a(31) = '1') then return( "111111111111" & a(19 downto 12)& a(20) & a(30 downto 21) & '0');
        else return( "000000000000" & a(19 downto 12) & a(20) & a(30 downto 21) & '0');
        end if;
        end function SIGN_EXTENDED_J;
--
      function SIGN_EXTENDED_S(a: in STD_LOGIC_VECTOR ) return STD_LOGIC_VECTOR is
        begin
         if (a(31) = '1') then return( "111111111111111111111" & a(30 downto 25)&a(11 downto 7));
        else return( "000000000000000000000" & a(30 downto 25)&a(11 downto 7));
        end if;
        end function SIGN_EXTENDED_S;
--
      function SHIFTED_U(a: in STD_LOGIC_VECTOR ) return STD_LOGIC_VECTOR is
        begin
         return(a(31 downto 12) & "000000000000");
        end function SHIFTED_U;
--
      function SIGN_EXTENDED_8(a: in SIGNED) return SIGNED is
        begin
         if (a(7) = '1') then return("1111111111111111111111111" & a(6 downto 0));
        else return("0000000000000000000000000" & a(6 downto 0));
        end if;
        end function SIGN_EXTENDED_8;
--
      function SIGN_EXTENDED_16(a: in SIGNED ) return SIGNED is
        begin
         if (a(15) = '1') then return("11111111111111111" & a(14 downto 0));
        else return("00000000000000000" & a(14 downto 0));
        end if;
        end function SIGN_EXTENDED_16;
--
      function ZERO_EXTENDED_8(a: in SIGNED ) return SIGNED is
        begin
        return("000000000000000000000000" & a(7 downto 0));
        end function ZERO_EXTENDED_8;
--
      function ZERO_EXTENDED_16(a: in SIGNED ) return SIGNED is
        begin
        return("0000000000000000" & a(15 downto 0));
        end function ZERO_EXTENDED_16;
--
      function SLT(a,b: in SIGNED ) return SIGNED is
        begin
        if a < b then
           return ("00000000000000000000000000000001");
        else
           return("00000000000000000000000000000000");
        end if;
        end function SLT;
--
      function SLTU(a,b: in SIGNED ) return SIGNED is
        begin
        if unsigned(a) < unsigned(b) then
           return ("00000000000000000000000000000001");
        else
           return("00000000000000000000000000000000");
        end if;
        end function SLTU;
--
    begin
--
   PORTA <= signed(PORT_A_in);
   ADDRESS_BUS <= std_logic_vector(PC);
   INSTRUCTION <= DATA_BUS;
--
-- Synchronous assertion and asynchronous de-assertion of the system Reset
--------------------------------------------------------------------------
SYNC_RES: process (CLK, RST)
begin
if RST = '0' then
   sys_RES <= '0';
   sinc_T1 <= '0';
   sinc_T2 <= '0';
   sinc_T3 <= '0';
else -- RST = '1'
   if rising_edge(CLK) then
      sinc_T1 <= '1';
      sinc_T2 <= sinc_T1;
      sinc_T3 <= sinc_T2;
        -- System Reset when hardware reset is stable for 3 clocks
         if sinc_T1 = '1' AND sinc_T2 = '1' AND sinc_T3 = '1' then
            sys_RES <= '1';
         end if;
   end if;
end if; -- RST
end process SYNC_RES;
--
--
-- STALL Processor
--------------------------------------------------------------------------
STALL_GEN: process (CLK, RST)
begin
if RST = '0' then
   STAGE_ENABLE <= (others => '0');
   PC <= X"0000_0000";
else -- RST = '1'
   if rising_edge(CLK) then
      case STAGE_ENABLE is
        when "000" => STAGE_ENABLE <= "001";
       when "001" => STAGE_ENABLE <= "011"; PC <= PC + 4; -- Increment the Program Counter
       when "011" => STAGE_ENABLE <= "111"; PC <= PC + 4; -- Increment the Program Counter
       when others => if PC_WRITE='1' then
                       PC <= RESULT(31 downto 1) & '0'; 
                     STAGE_ENABLE <= (others => '0');
                     else
                    PC <= PC + 4; -- Increment the Program Counter
                     end if;
     end case;
   end if; --CLK
end if; -- RST
end process STALL_GEN;
--
--
-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> PIPELINE STAGE 1 <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> ENCODING <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
--
Stage_1: process (CLK, sys_RES, STAGE_ENABLE(0))
begin
if sys_RES = '0' then
   RS1_REG <= '0';
   RS2_REG <= '0';
else -- sys_RES = '1'
if rising_edge(CLK) and (STAGE_ENABLE(0)='1') then
      DESTINATION <= INSTRUCTION(11 downto 7);  -- Extracting the store destination from the instruction
     SOURCE_REGISTER_1 <= INSTRUCTION(19 downto 15); -- Source Register 1 is passed to Pipeline Stage 2
      SOURCE_REGISTER_2 <= INSTRUCTION(24 downto 20); -- Source Register 2 is passed to Pipeline Stage 2
     RS1_REG <= '0';  -- ARGUMENT1 is a X register unless otherwise stated in the SM below
      RS2_REG <= '0';  -- ARGUMENT2 is a X register unless otherwise stated in the SM below
     JAL_FLG <= '0';  -- JAL instruction flag cleared by default
      case INSTRUCTION(6 downto 2) is   -- Encoding the operand
         when "00000"               =>  --=========================== LOAD opcode
            ARGUMENT3 <= signed(sign_extended_I(INSTRUCTION)); -- ARGUMENT 3 is I-Immediate
            OPERATION <= o_LOAD;
            case INSTRUCTION(14 downto 12) is -- Encoding func.3
               when "001"            =>  ------------------------ LH
                                         DATA_FORMAT <= l_16;
               when "010"            =>  ------------------------ LW
                                         DATA_FORMAT <= l_32;
               when "100"            =>  ------------------------ LBU
                                         DATA_FORMAT <= l_8_U;
               when "101"            =>  ------------------------ LHU
                                         DATA_FORMAT <= l_16_U;
               when others           =>  ------------------------ LB ("000")
                                         DATA_FORMAT <= l_8;
            end case;
         when "00011"               =>  --=========================== MISC_MEM opcode
            case INSTRUCTION(14 downto 12) is -- Encoding func.3         
               when "001"            =>  ------------------------ FENCEI
               when others           =>  ------------------------ FENCE ("000")
            end case;
         when "00100" | "01100"     =>  --=========================== OP-IMM / OP opcode
          if INSTRUCTION(19 downto 15)="00000" then ARGUMENT1 <= (others => '0'); else ARGUMENT1 <= X_REGISTER(to_integer(unsigned(INSTRUCTION(19 downto 15)))); end if;
          RS1_REG <= '1'; -- ARGUMENT1 is a X register
         if INSTRUCTION(5) = '0' then
                ARGUMENT2 <= signed(sign_extended_I(INSTRUCTION)); -- ARGUMENT2 is a I-Immediate
         else
            RS2_REG <= '1'; -- ARGUMENT2 is a X register
            if INSTRUCTION(24 downto 20)="00000" then ARGUMENT2 <= (others => '0'); else ARGUMENT2 <= X_REGISTER_MIRROR(to_integer(unsigned(INSTRUCTION(24 downto 20)))); end if;
         end if;
            case INSTRUCTION(14 downto 12) is -- Encoding func.3
               when "001"            =>  ------------------------ SLL/SLLI
                                         OPERATION <= o_SHIFT_LEFT;
               when "010"            =>  ------------------------ SLT/SLTI
                                         OPERATION <= o_SLT;
               when "011"            =>  ------------------------ SLT/SLTIU
                                         OPERATION <= o_SLTU;
               when "100"            =>  ------------------------ XOR/XORI
                                         OPERATION <= o_XOR;
               when "101"            =>  if INSTRUCTION(30) = '1' then
                                          ---------------------- SRA/SRAI;
                                          OPERATION <= o_SRA;
                                         else
                                    ---------------------- SRL/SRLI;
                                         OPERATION <= o_SHIFT_RIGHT;
                                         end if;
               when "110"            =>  ------------------------ OR/ORI
                                         OPERATION <= o_OR;
               when "111"            =>  ------------------------ AND/ANDI
                                         OPERATION <= o_AND;
               when others           =>  if INSTRUCTION(5) = '1' and INSTRUCTION(30) = '1' then
                                          ---------------------- SUB
                                          OPERATION <= o_SUB;
                                         else
                                    ---------------------- ADD/ADDI
                                          OPERATION <= o_SUM;
                                  end if;
            end case;
         when "00101"               =>  --=========================== AUIPC / OPCODE
                                          OPERATION <= o_SUM;
                                  ARGUMENT1 <= signed(shifted_U(INSTRUCTION)); -- ARGUMENT 1 is U_Immediate
                                  ARGUMENT2 <= PC;
         when "01000"               =>  --=========================== STORE opcode
            OPERATION <= o_SAVE;
         RS1_REG <= '1'; -- ARGUMENT1 is a X register
         if INSTRUCTION(19 downto 15)="00000" then ARGUMENT1 <= (others => '0'); else ARGUMENT1 <= X_REGISTER(to_integer(unsigned(INSTRUCTION(19 downto 15)))); end if;
         RS2_REG <= '1'; -- ARGUMENT2 is a X register
         if INSTRUCTION(24 downto 20)="00000" then ARGUMENT2 <= (others => '0'); else ARGUMENT2 <= X_REGISTER_MIRROR(to_integer(unsigned(INSTRUCTION(24 downto 20)))); end if;
         ARGUMENT3 <= signed (sign_extended_S(INSTRUCTION));
            case INSTRUCTION(14 downto 12) is
               when "000"            =>  ------------------------ SB
                                         DATA_FORMAT <= l_8_U;
               when "001"            =>  ------------------------ SH
                                         DATA_FORMAT <= l_16_U;
               when others           =>  ------------------------ SW ("010")
                                         DATA_FORMAT <= l_32;
            end case;
         when "01101"               =>  --=========================== LUI / OPCODE
                                  ARGUMENT1 <= signed(shifted_U(INSTRUCTION)); -- ARGUMENT 1 is U_Immediate
                                  ARGUMENT2 <= (others => '0');
                                  OPERATION <= o_SUM;
         when "11000"               =>  --=========================== BRANCH opcode
          ARGUMENT3 <= signed (sign_extended_S(INSTRUCTION)) + X_REGISTER(to_integer(unsigned(INSTRUCTION(19 downto 15))));
            case INSTRUCTION(14 downto 12) is -- Encoding func.3
               when "001"            =>  ------------------------ BNE
                                         OPERATION <= o_BNE;
               when "100"            =>  ------------------------ BLT
                                         OPERATION <= o_BLT;
               when "101"            =>  ------------------------ BGE
                                         OPERATION <= o_BGE;
               when "110"            =>  ------------------------ BLTU
                                         OPERATION <= o_BLTU;
               when "111"            =>  ------------------------ BGEU
                                         OPERATION <= o_BGEU;
               when others           =>  ------------------------ BEQ ("000")
                                         OPERATION <= o_BEQ;
            end case;
         when "11001"               =>  --=========================== JALR / OPCODE
                                  ARGUMENT2 <= signed(sign_extended_I(INSTRUCTION)); -- ARGUMENT 2 is I-Immediate
                                  OPERATION <= o_SUM;
         when "11011"               =>  --=========================== JAL / OPCODE
                                           JAL_FLG <= '1';
                                  ARGUMENT1 <= signed (sign_extended_J(INSTRUCTION)); -- ARGUMENT 1 is J-IMMEDIATE
                                             ARGUMENT2 <= PC;
                                  OPERATION <= o_SUM;
         when "11100"               =>  --=========================== SYSTEM opcode
            case INSTRUCTION(14 downto 12) is -- Encoding func.3
               when "000"            =>
                 case INSTRUCTION(25)is  -- Encoding func.7
                  when '0'          =>  ------------------------ ECALL
                  when '1'          =>  ------------------------ EBREAK
                  when others       =>  NULL;
                 end case;
               when "001"            =>  ------------------------ CSRRW
               when "010"            =>  ------------------------ CSRRS
               when "011"            =>  ------------------------ CSRRC
               when "101"            =>  ------------------------ CSRRWI
               when "110"            =>  ------------------------ CSRRSI
               when "111"            =>  ------------------------ CSRRCI
               when others           =>  NULL;
            end case;
         when others                =>  NULL;
      end case;
    --
end if; -- rising edge (CLK)
end if; -- sys_RES
end process Stage_1;
--
--
--
-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> PIPELINE STAGE 2 <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> EXECUTING <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
--
--
Stage_2_pre_proc: process (RS1_REG, RS1_REG_ST3, RS2_REG, RS2_REG_ST3, RS1_REG_ST4, RS2_REG_ST4)
begin
if sys_RES = '0' then
   ARBIT <= (others => '0');
else  -- sys_RES = '1'
   -- processor stores and reads from the src1 register, ALU result is used as an input instead
    if ((STORE_REGISTER = SOURCE_REGISTER_1) and (RS1_REG = '1') and (RS1_REG_ST3 = '1')) then ARBIT <= "001";
   -- processor stores and reads from the src2 register, ALU result is used as an input instead
   elsif ((STORE_REGISTER = SOURCE_REGISTER_2) and (RS2_REG = '1') and (RS2_REG_ST3 = '1')) then ARBIT <= "010";
   -- processor stores and reads from the src1 register after one instruction (still no time for store to complete)
    elsif ((STORE_REGISTER_2 = SOURCE_REGISTER_1) and (RS1_REG = '1') and (RS1_REG_ST4 = '1')) then ARBIT <= "011";
   -- processor stores and reads from the src2 register after one instruction (still no time for store to complete)
   elsif ((STORE_REGISTER_2 = SOURCE_REGISTER_2) and (RS2_REG = '1') and (RS2_REG_ST4 = '1')) then ARBIT <= "100";
   else ARBIT <= (others => '0');
   end if;
end if; -- sys_RES
end process Stage_2_pre_proc;
--
Stage_2: process (CLK, sys_RES, STAGE_ENABLE(1))
begin
if sys_RES = '0' then
   RS1_REG_ST3 <= '0';
   RS2_REG_ST3 <= '0';
else  -- sys_RES = '1'
if rising_edge(CLK) then
  PC_WRITE <= '0';
  if (STAGE_ENABLE(1)='1') then
      STORE_REGISTER <= DESTINATION; -- Passes the Store Destination from Stage 1 to Stage 3
      RS1_REG_ST3 <= RS1_REG; -- Bypass condition flag
      RS2_REG_ST3 <= RS2_REG; -- Bypass condition flag
     DATA_FORMAT_2 <= DATA_FORMAT; -- Passes the Load format from Stage 1 to Stage 3
      MEM_STORE <= '0'; -- the instruction result is stored in a STORE_REGISTER by default
      LOAD_OP <= '0';   -- no Load Operation flag by default
      -- if the RESULT of the previous operation is going to be stored into the same register as ARGUMENT1 
      -- then the RESULT is used instead as an input of the operation (Bypassing)
         case OPERATION is
           when o_SUM         => if JAL_FLG = '1' then PC_WRITE <= '1'; end if;
                                case ARBIT is
                                when "001" => RESULT(31 downto 0) <= RESULT + ARGUMENT2;
                                when "010" => RESULT(31 downto 0) <= ARGUMENT1 + RESULT;
                              when "011" => RESULT(31 downto 0) <= POST_RESULT + ARGUMENT2;
                                when "100" => RESULT(31 downto 0) <= ARGUMENT1 + POST_RESULT;
                                when others => RESULT(31 downto 0) <= ARGUMENT1 + ARGUMENT2;
                             end case;
           when o_SUB         => case ARBIT is
                                    when "001" => RESULT(31 downto 0) <= RESULT - ARGUMENT2;
                              when "010" => RESULT(31 downto 0) <= ARGUMENT1 - RESULT;
                              when "011" => RESULT(31 downto 0) <= POST_RESULT - ARGUMENT2;
                                when "100" => RESULT(31 downto 0) <= ARGUMENT1 - POST_RESULT;
                              when others => RESULT(31 downto 0) <= ARGUMENT1 - ARGUMENT2;
                                 end case;
           when o_SHIFT_LEFT  => case ARBIT is
                                    when "001" => RESULT(31 downto 0) <= shift_left(RESULT, to_integer(ARGUMENT2(4 downto 0)));
                                    when "010" => RESULT(31 downto 0) <= shift_left(ARGUMENT1, to_integer(RESULT(4 downto 0)));
                              when "011" => RESULT(31 downto 0) <= shift_left(POST_RESULT, to_integer(ARGUMENT2(4 downto 0)));
                                    when "100" => RESULT(31 downto 0) <= shift_left(ARGUMENT1, to_integer(POST_RESULT(4 downto 0)));
                                    when others => RESULT(31 downto 0) <= shift_left(ARGUMENT1, to_integer(ARGUMENT2(4 downto 0)));
                                 end case;
           when o_SHIFT_RIGHT => case ARBIT is
                                    when "001" => RESULT(31 downto 0) <= shift_right(RESULT, to_integer(ARGUMENT2(4 downto 0)));
                                    when "010" => RESULT(31 downto 0) <= shift_right(ARGUMENT1, to_integer(RESULT(4 downto 0)));
                              when "011" => RESULT(31 downto 0) <= shift_right(POST_RESULT, to_integer(ARGUMENT2(4 downto 0)));
                                    when "100" => RESULT(31 downto 0) <= shift_right(ARGUMENT1, to_integer(POST_RESULT(4 downto 0)));
                                    when others => RESULT(31 downto 0) <= shift_right(ARGUMENT1, to_integer(ARGUMENT2(4 downto 0)));
                                 end case;
      --     when o_SRA         => RESULT(31 downto 0) <= RESULT sra to_integer(ARGUMENT2(4 downto 0)) when ARBIT <= "01" else
      --                                                 ARGUMENT1 sra to_integer(RESULT(4 downto 0)) when ARBIT <= "10" else
      --                                                ARGUMENT1 sra to_integer(ARGUMENT2(4 downto 0));
           when o_AND         => case ARBIT is
                                    when "001" => RESULT(31 downto 0) <= RESULT AND ARGUMENT2;
                                    when "010" => RESULT(31 downto 0) <= ARGUMENT1 AND RESULT;
                              when "011" => RESULT(31 downto 0) <= POST_RESULT AND ARGUMENT2;
                                when "100" => RESULT(31 downto 0) <= ARGUMENT1 AND POST_RESULT;
                                    when others => RESULT(31 downto 0) <= ARGUMENT1 AND ARGUMENT2;
                                 end case;
           when o_OR          => case ARBIT is
                                    when "001" => RESULT(31 downto 0) <= RESULT OR ARGUMENT2;
                                    when "010" => RESULT(31 downto 0) <= ARGUMENT1 OR RESULT;
                              when "011" => RESULT(31 downto 0) <= POST_RESULT OR ARGUMENT2;
                                when "100" => RESULT(31 downto 0) <= ARGUMENT1 OR POST_RESULT;
                                    when others => RESULT(31 downto 0) <= ARGUMENT1 OR ARGUMENT2;
                                 end case;
           when o_XOR         => case ARBIT is
                                    when "001" => RESULT(31 downto 0) <= RESULT XOR ARGUMENT2;
                                    when "010" => RESULT(31 downto 0) <= ARGUMENT1 XOR RESULT;
                              when "011" => RESULT(31 downto 0) <= POST_RESULT XOR ARGUMENT2;
                                when "100" => RESULT(31 downto 0) <= ARGUMENT1 XOR POST_RESULT;
                                    when others => RESULT(31 downto 0) <= ARGUMENT1 XOR ARGUMENT2;
                                 end case;
           when o_SLT         => RESULT(31 downto 0) <= SLT(RESULT, ARGUMENT2);
           when o_SLTU        => RESULT(31 downto 0) <= SLTU(RESULT, ARGUMENT2);
           when o_LOAD        => LOAD_OP <= '1';               -- sets the Load Operation flag for Stage 3
                                 if (ARGUMENT3) = 0 then  RESULT <= ZERO_EXTENDED_8(PORTA);
                                 else RESULT <= signed(USER_MEM(to_integer(ARGUMENT3)));
                                 end if;
           when o_SAVE        => MEM_STORE <= '1'; -- result is stored in the user RAM memory
                                 OP_ADDRESS <= RESULT + ARGUMENT3;
                           case DATA_FORMAT is
                                   when l_16_U =>  RESULT <= ZERO_EXTENDED_16(ARGUMENT2);
                                   when l_8_U  =>  RESULT <= ZERO_EXTENDED_8(ARGUMENT2);
                                   when others =>  RESULT <= ARGUMENT2; -- l_32
                                 end case;
           when o_BEQ         => if ARGUMENT1 = ARGUMENT2 then RESULT <= ARGUMENT3; PC_WRITE <= '1'; end if;
           when o_BNE         => if ARGUMENT1 /= ARGUMENT2 then RESULT <= ARGUMENT3; PC_WRITE <= '1'; end if;
           when o_BLT         => if ARGUMENT1 < ARGUMENT2 then RESULT <= ARGUMENT3; PC_WRITE <= '1'; end if;
           when o_BGE         => if ARGUMENT1 > ARGUMENT2 then RESULT <= ARGUMENT3; PC_WRITE <= '1'; end if;
           when o_BLTU        => if unsigned(ARGUMENT1) < unsigned(ARGUMENT2) then RESULT <= ARGUMENT3; PC_WRITE <= '1'; end if;
           when o_BGEU        => if unsigned(ARGUMENT1) > unsigned(ARGUMENT2) then RESULT <= ARGUMENT3; PC_WRITE <= '1'; end if;
           when others        => NULL;
          end case;
  end if; -- STAGE_ENABLE(1)
end if; -- rising edge (CLK)
end if; -- sys_RES
end process Stage_2;
--
--
-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> PIPELINE STAGE 3 <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>  SAVING  <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
--
Stage_3: process (CLK, sys_RES, STAGE_ENABLE(2))
begin
if sys_RES = '0' then
   NULL;
else
if rising_edge(CLK) and STAGE_ENABLE(2) = '1' then
     POST_RESULT <= RESULT;
     STORE_REGISTER_2 <= STORE_REGISTER;
     RS1_REG_ST4 <= RS1_REG_ST3; -- Bypass condition flag
      RS2_REG_ST4 <= RS2_REG_ST3; -- Bypass condition flag
      if (MEM_STORE = '0') then -- Result is stored in STORE_REGISTER
         if LOAD_OP = '0' then
                if J_PP = '0' then
                 X_REGISTER(to_integer(unsigned(STORE_REGISTER))) <= RESULT;
                 X_REGISTER_MIRROR(to_integer(unsigned(STORE_REGISTER))) <= RESULT;
                else
                 X_REGISTER(to_integer(unsigned(STORE_REGISTER))) <= RESULT(31 downto 1) & '0';
                 X_REGISTER_MIRROR(to_integer(unsigned(STORE_REGISTER))) <= RESULT(31 downto 1) & '0';
                end if;
         else
              case DATA_FORMAT_2 is
               when l_32 =>
                    X_REGISTER(to_integer(unsigned(STORE_REGISTER))) <= RESULT;
                    X_REGISTER_MIRROR(to_integer(unsigned(STORE_REGISTER))) <= RESULT;
               when l_16 =>
                    X_REGISTER(to_integer(unsigned(STORE_REGISTER))) <= SIGN_EXTENDED_16(RESULT);
                    X_REGISTER_MIRROR(to_integer(unsigned(STORE_REGISTER))) <= SIGN_EXTENDED_16(RESULT);
               when l_8 =>
                    X_REGISTER(to_integer(unsigned(STORE_REGISTER))) <= SIGN_EXTENDED_8(RESULT);
                    X_REGISTER_MIRROR(to_integer(unsigned(STORE_REGISTER))) <= SIGN_EXTENDED_8(RESULT);
               when l_16_U =>
                    X_REGISTER(to_integer(unsigned(STORE_REGISTER))) <= ZERO_EXTENDED_16(RESULT);
                    X_REGISTER_MIRROR(to_integer(unsigned(STORE_REGISTER))) <= ZERO_EXTENDED_16(RESULT);
               when l_8_U =>
                    X_REGISTER(to_integer(unsigned(STORE_REGISTER))) <= ZERO_EXTENDED_8(RESULT);
                    X_REGISTER_MIRROR(to_integer(unsigned(STORE_REGISTER))) <= ZERO_EXTENDED_8(RESULT);
               when others => NULL;
             end case;
         end if; --LOAD_OP
      else -- Result is stored in user RAM
         if OP_ADDRESS = 0 then -- PORT B is an 8 bit output only and is memory mapped at address 0 (User RAM)
            PORT_B_out <= std_logic_vector(RESULT(7 downto 0));
         else
            USER_MEM(to_integer(unsigned(OP_ADDRESS))) <= std_logic_vector(RESULT);
         end if;
      end if; -- MEM_STORE
end if; -- rising edge (CLK)
end if; -- sys_RES
end process Stage_3;
--
--
end Behavioral;



И съответно тест бенча по-надолу, с вградения фърмуеър за тестване на процесора:

Код:
-- Started: 06/12/2022
-- Last modified:
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
--USE std.textio.all;
--USE ieee.std_logic_textio.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY RISCV_Test IS
END RISCV_Test;

ARCHITECTURE behavior OF RISCV_Test IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT RISC_V_Core
    Port ( RST                 : in    std_logic;                       -- Reset signal
          PORT_A_in             : in    std_logic_vector(7 downto 0);    -- PORT A - only inputs
           PORT_B_out            : out   std_logic_vector(7 downto 0);    -- PORT B - only outputs
         CLK                   : in    std_logic;                       -- Clock signal
         ADDRESS_BUS           : out   std_logic_vector(31 downto 0);   -- port declaration of bidirectional data line
         DATA_BUS              : in    std_logic_vector(31 downto 0)    -- port declaration of bidirectional data line
     );
    END COMPONENT;

    type RAM_MEM_1 is array (0 to 2047) of std_logic_vector(31 downto 0);
    signal   PROG_MEM              : RAM_MEM_1 :=
    (X"00000293",X"00028303",X"00100393",X"00000013",X"00628023",X"fedff06f",X"00000013",X"00000013",X"00000013",X"00000013",X"00000013",X"00000013",X"00000013",X"00000013",X"00000013",X"00000013",
     X"00000013",X"00000013",X"00000013",X"00000013",X"00000013",X"00000013",X"00000013",X"00000013",X"00000013",X"00000013",X"00000013",X"00000013",X"00000013",X"00000013",X"00000013",X"00000013",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
     X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000"
    );

   --Inputs
   signal CLOCK                : std_logic := '0';
   signal RESET                : std_logic := '0';
   signal INSTR_ADDRESS        : std_logic_vector(31 downto 0);
   signal PORTA                : std_logic_vector(7 downto 0) := "00000001";

   --Outputs
   signal PORTB                : std_logic_vector(7 downto 0);
   signal INSTR_DATA           : std_logic_vector(31 downto 0);

   -- Clock period definitions
   constant CLK_period   : time := 50 ns; -- 20 MHz Clock Frequency

BEGIN

   -- Instantiate the Unit Under Test (UUT)
   uut: RISC_V_Core PORT MAP (
         RST           =>  RESET,
        PORT_A_in     =>  PORTA,
         PORT_B_out    =>  PORTB,
       CLK           =>  CLOCK,
       ADDRESS_BUS   =>  INSTR_ADDRESS,
       DATA_BUS      =>  INSTR_DATA
        );

   -- Clock process definitions
   CLK_process :process
   begin
      CLOCK <= '0';
    INSTR_DATA <= PROG_MEM(to_integer(unsigned(INSTR_ADDRESS(31 downto 2))));
      wait for CLK_period/2;
      CLOCK <= '1';
      wait for CLK_period/2;
   end process;

   -- Stimulus process

   stim_proc: process
   begin
        wait for 100 ns;
      RESET <= '1';
        wait for 1100 ns;
    PORTA <= "00000010";
        wait for 1100 ns;
    PORTA <= "00000100";
        wait for 1100 ns;
    PORTA <= "00001000";
        wait for 1100 ns;
    PORTA <= "00010000";
        wait;
   end process stim_proc;

END;


Вто Май 02, 2023 10:38 pm
Профил
Ранг: Форумен бог
Ранг: Форумен бог
Аватар

Регистриран на: Сря Апр 27, 2005 11:48 am
Мнения: 4760
Мнение Re: RISC-V
без задни мисли имам един въпрос:
Какъв е смисъла да "копаете" в първите 10% на RISC-V
самообучение? спортна злоба? чесане на краста?
мислите някакъв частен случай на чип "дзвер" ? .... реално, икономически не изгоден

_________________
main[-1u]={1};


Чет Май 04, 2023 4:55 pm
Профил ICQ
Ранг: Почетен член
Ранг: Почетен член
Аватар

Регистриран на: Съб Сеп 03, 2005 10:31 am
Мнения: 748
Местоположение: Пловдив
Мнение Re: RISC-V
TheWizard написа:
без задни мисли имам един въпрос:
Какъв е смисъла да "копаете" в първите 10% на RISC-V
самообучение? спортна злоба? чесане на краста?
мислите някакъв частен случай на чип "дзвер" ? .... реално, икономически не изгоден


Когато целият ти дизайн на устройството е оновно в FPGA ама ти трябва User шаренотия не , е много удачно да го правиш на VHDL или подобми и тогава е най лесно и удобно да си синтезираш вътре един малък процесор който да върши черната работа особено ако имаш ресурси в FPGA-то.
Поне така правя аз макар че ползвам друг процесор не RISK-V просто защото когато започнах така Risk-V оюе го нямаше .
Е то почнаха да добавят и процесори в ФПГА-а та така че и тва почна да губи смисъл де .

_________________
"I really do like SOLDERING as my programming language." Bob Pease


Чет Май 04, 2023 5:15 pm
Профил ICQ
Ранг: Форумен бог
Ранг: Форумен бог

Регистриран на: Вто Ное 06, 2018 4:18 pm
Мнения: 1312
Мнение Re: RISC-V
Ами не, не си губи смисъла, особенно напоследък, когато започнаха да изчезват от пазара всякакви процесори - значи проектираш си контролер, правиш го популярен продукт и изведнъж процесора изчезва от пазара, казват ти 60 седмици доставка а през това време губиш клиентела. преправяш платката да става за друг процесор ама и той изчезва и така, докато не остане нищо читаво, през това време складираш неизползваеми платки без процесори. А когато си проектираш сам процесора може да си вкараш всичките периферии вътре - серийни интерфейси, PWM, PID контролер, таймери, включително копроцесор за управление на дисплея, правиш си отделна платка за процесора само, за да може да я преработиш бързо и евтино ако FPGA-to изчезне от пазара, а сега има и нов играч - Efinix, с доста мощни FPGA, които са достъпни. Това е точно като да си направиш сам регулатор на напрежение с операционен усилвател и транзистор вместо там разните му LM-и и 78-ци.


Чет Май 04, 2023 11:52 pm
Профил
Ранг: Форумен бог
Ранг: Форумен бог

Регистриран на: Сря Юли 26, 2006 11:15 am
Мнения: 1263
Местоположение: Phoenix AZ
Мнение Re: RISC-V
Bai Ui написа:
Ами не, не си губи смисъла, особенно напоследък, когато започнаха да изчезват от пазара всякакви процесори - значи проектираш си контролер, правиш го популярен продукт и изведнъж процесора изчезва от пазара, казват ти 60 седмици доставка а през това време губиш клиентела. преправяш платката да става за друг процесор ама и той изчезва и така, докато не остане нищо читаво, през това време складираш неизползваеми платки без процесори. А когато си проектираш сам процесора може да си вкараш всичките периферии вътре - серийни интерфейси, PWM, PID контролер, таймери, включително копроцесор за управление на дисплея, правиш си отделна платка за процесора само, за да може да я преработиш бързо и евтино ако FPGA-to изчезне от пазара, а сега има и нов играч - Efinix, с доста мощни FPGA, които са достъпни. Това е точно като да си направиш сам регулатор на напрежение с операционен усилвател и транзистор вместо там разните му LM-и и 78-ци.


Ами до известна степен съгласен , но пък ако ти трябва твой МЦУ то ASIC се правят от много време.... последно преди 7-8 г даже бях на интервю при едни такива дето за 10к ти сковават МЦУ то ... сега предполагам е повече ... не съм гледал.
Ама за тогава цената беше супер щото винаги има поне 2 неща дето все се питат когат се започва нещо-
1- колкото и да търсиш и да има МЦУ та то все нещо не пасва - или е в повече или недостига или нещо друго.
2-ако си сковеш ASIC ( които си е нормално МЦУ само дет е дефинирано от хората дето уж знаят какво искат) до няква степен си пазиш ИП то .

Другото вече е кои физически ще ги прави - тука вече си е съвсем друга материя и там не ми се влиза.


Съб Май 13, 2023 6:36 am
Профил
Ранг: Форумен бог
Ранг: Форумен бог

Регистриран на: Вто Ное 06, 2018 4:18 pm
Мнения: 1312
Мнение Re: RISC-V
Ами да, дори готовите ИП-та често не пасват на изискванията, особенно тези дето са на модулен принцип с Уишбоун или AXI шини. Имат си предимства, особенно при многоядрените архитектури ама там както спомена вече нещата идват в повече.


Съб Май 13, 2023 12:57 pm
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