 | Код: void hal_enable_PWM( void ) { /* TM - created with PE */ /* SIM_SCGC6: FTM1=1 */ SIM_SCGC6 |= SIM_SCGC6_FTM1_MASK; (void)(FTM1_SC == 0U); /* Dummy read of the FTM1_SC register to clear the interrupt flag */ /* FTM1_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TOF=0,TOIE=0,CPWMS=0,CLKS=0,PS=0 */ FTM1_SC = (FTM_SC_CLKS(0x00) | FTM_SC_PS(0x00)); /* Stop the counter */ (void)(FTM1_C0SC == 0U); /* Dummy read of the FTM1_C0SC register to clear the interrupt flag */ (void)(FTM1_C1SC == 0U); /* Dummy read of the FTM1_C1SC register to clear the interrupt flag */ /* FTM1_MODE: WPDIS=1 */ FTM1_MODE |= FTM_MODE_WPDIS_MASK; /* Disable write protection */ /* FTM1_C0SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM1_C0SC = 0x00U; /* FTM1_C1SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM1_C1SC = 0x00U; /* FTM1_SC: TOF=0,CPWMS=0 */ FTM1_SC &= (uint32_t)~(uint32_t)((FTM_SC_TOF_MASK | FTM_SC_CPWMS_MASK)); /* FTM1_MODE: FTMEN=1 */ FTM1_MODE |= FTM_MODE_FTMEN_MASK; /* FTM1_INVCTRL: INV0EN=0 */ FTM1_INVCTRL &= (uint32_t)~(uint32_t)(FTM_INVCTRL_INV0EN_MASK); /* FTM1_COMBINE: FAULTEN0=0,SYNCEN0=0,DTEN0=1,DECAPEN0=0,COMP0=1,COMBINE0=1 */ FTM1_COMBINE = (uint32_t)((FTM1_COMBINE & (uint32_t)~(uint32_t)( FTM_COMBINE_FAULTEN0_MASK | FTM_COMBINE_SYNCEN0_MASK | FTM_COMBINE_DECAPEN0_MASK )) | (uint32_t)( FTM_COMBINE_DTEN0_MASK | FTM_COMBINE_COMP0_MASK | FTM_COMBINE_COMBINE0_MASK )); /* FTM1_C0SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,ELSB=1,ELSA=0,??=0,DMA=0 */ FTM1_C0SC = (uint32_t)((FTM1_C0SC & (uint32_t)~(uint32_t)( FTM_CnSC_CHF_MASK | FTM_CnSC_CHIE_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_DMA_MASK | 0xFFFFFF02U )) | (uint32_t)( FTM_CnSC_ELSB_MASK )); /* FTM1_C1SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,ELSB=1,ELSA=0,??=0,DMA=0 */ FTM1_C1SC = (uint32_t)((FTM1_C1SC & (uint32_t)~(uint32_t)( FTM_CnSC_CHF_MASK | FTM_CnSC_CHIE_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_DMA_MASK | 0xFFFFFF02U )) | (uint32_t)( FTM_CnSC_ELSB_MASK )); /* FTM1_C0V: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,VAL=0 */ FTM1_C0V = FTM_CnV_VAL(0x00); /* FTM1_C1V: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,VAL=0x96 */ FTM1_C1V = FTM_CnV_VAL(0x96); /* FTM1_POL: POL1=0,POL0=0 */ FTM1_POL &= (uint32_t)~(uint32_t)((FTM_POL_POL1_MASK | FTM_POL_POL0_MASK)); /* FTM1_FILTER: CH1FVAL=0,CH0FVAL=0 */ FTM1_FILTER &= (uint32_t)~(uint32_t)( FTM_FILTER_CH1FVAL(0x0F) | FTM_FILTER_CH0FVAL(0x0F) ); /* FTM1_OUTINIT: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CH1OI=0,CH0OI=0 */ FTM1_OUTINIT &= (uint32_t)~(uint32_t)( FTM_OUTINIT_CH1OI_MASK | FTM_OUTINIT_CH0OI_MASK | 0xFFFFFF00U ); /* FTM1_OUTMASK: CH1OM=0,CH0OM=0 */ FTM1_OUTMASK &= (uint32_t)~(uint32_t)( FTM_OUTMASK_CH1OM_MASK | FTM_OUTMASK_CH0OM_MASK ); /* FTM1_FLTCTRL: FFVAL=0 */ FTM1_FLTCTRL &= (uint32_t)~(uint32_t)(FTM_FLTCTRL_FFVAL(0x0F)); /* FTM1_FLTPOL: FLT2POL=0,FLT1POL=0,FLT0POL=0 */ FTM1_FLTPOL &= (uint32_t)~(uint32_t)( FTM_FLTPOL_FLT2POL_MASK | FTM_FLTPOL_FLT1POL_MASK | FTM_FLTPOL_FLT0POL_MASK ); /* FTM1_FLTCTRL: FFLTR2EN=0,FFLTR1EN=0,FFLTR0EN=0,FAULT2EN=0,FAULT1EN=0,FAULT0EN=0 */ FTM1_FLTCTRL &= (uint32_t)~(uint32_t)( FTM_FLTCTRL_FFLTR2EN_MASK | FTM_FLTCTRL_FFLTR1EN_MASK | FTM_FLTCTRL_FFLTR0EN_MASK | FTM_FLTCTRL_FAULT2EN_MASK | FTM_FLTCTRL_FAULT1EN_MASK | FTM_FLTCTRL_FAULT0EN_MASK ); /* FTM1_SYNC: SWSYNC=0,TRIG2=0,TRIG1=0,TRIG0=0,SYNCHOM=0,REINIT=0,CNTMAX=0,CNTMIN=0 */ FTM1_SYNC &= (uint32_t)~(uint32_t)( FTM_SYNC_SWSYNC_MASK | FTM_SYNC_TRIG2_MASK | FTM_SYNC_TRIG1_MASK | FTM_SYNC_TRIG0_MASK | FTM_SYNC_SYNCHOM_MASK | FTM_SYNC_REINIT_MASK | FTM_SYNC_CNTMAX_MASK | FTM_SYNC_CNTMIN_MASK ); /* FTM1_EXTTRIG: INITTRIGEN=0,CH1TRIG=0,CH0TRIG=0 */ FTM1_EXTTRIG &= (uint32_t)~(uint32_t)( FTM_EXTTRIG_INITTRIGEN_MASK | FTM_EXTTRIG_CH1TRIG_MASK | FTM_EXTTRIG_CH0TRIG_MASK ); /* FTM1_MOD: MOD=0x012C */ FTM1_MOD = (uint32_t)((FTM1_MOD & (uint32_t)~(uint32_t)( FTM_MOD_MOD(0xFED3) )) | (uint32_t)( FTM_MOD_MOD(0x012C) )); /* FTM1_CNTIN: INIT=0 */ FTM1_CNTIN &= (uint32_t)~(uint32_t)(FTM_CNTIN_INIT(0xFFFF)); /* FTM1_DEADTIME: DTPS=0,DTVAL=0x14 */ FTM1_DEADTIME = (uint32_t)((FTM1_DEADTIME & (uint32_t)~(uint32_t)( FTM_DEADTIME_DTPS(0x03) | FTM_DEADTIME_DTVAL(0x2B) )) | (uint32_t)( FTM_DEADTIME_DTVAL(0x14) )); /* FTM1_CNT: COUNT=0 */ FTM1_CNT &= (uint32_t)~(uint32_t)(FTM_CNT_COUNT(0xFFFF)); /* FTM1_MODE: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,FAULTIE=0,FAULTM=0,PWMSYNC=0,INIT=0,FTMEN=1 */ FTM1_MODE = (uint32_t)((FTM1_MODE & (uint32_t)~(uint32_t)( FTM_MODE_FAULTIE_MASK | FTM_MODE_FAULTM(0x03) | FTM_MODE_PWMSYNC_MASK | FTM_MODE_INIT_MASK | 0xFFFFFF00U )) | (uint32_t)( FTM_MODE_FTMEN_MASK )); /* FTM1_SYNCONF: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,SYNCMODE=0,??=0,SWOC=0,INVC=0,??=0,CNTINC=0,??=0,HWTRIGMODE=0 */ FTM1_SYNCONF &= (uint32_t)~(uint32_t)( FTM_SYNCONF_SYNCMODE_MASK | FTM_SYNCONF_SWOC_MASK | FTM_SYNCONF_INVC_MASK | FTM_SYNCONF_CNTINC_MASK | FTM_SYNCONF_HWTRIGMODE_MASK | 0xFFE0E04AU ); /* FTM1_SC: TOF=0,TOIE=0,CPWMS=0,CLKS=1,PS=0 */ FTM1_SC = (uint32_t)((FTM1_SC & (uint32_t)~(uint32_t)( FTM_SC_TOF_MASK | FTM_SC_TOIE_MASK | FTM_SC_CPWMS_MASK | FTM_SC_CLKS(0x02) | FTM_SC_PS(0x07) )) | (uint32_t)( FTM_SC_CLKS(0x01) )); /* FTM1_FMS: FAULTF=0,WPEN=0,FAULTF3=0,FAULTF2=0,FAULTF1=0,FAULTF0=0 */ FTM1_FMS &= (uint32_t)~(uint32_t)( FTM_FMS_FAULTF_MASK | FTM_FMS_WPEN_MASK | FTM_FMS_FAULTF3_MASK | FTM_FMS_FAULTF2_MASK | FTM_FMS_FAULTF1_MASK | FTM_FMS_FAULTF0_MASK ); /* FTM1_QDCTRL: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,PHAFLTREN=0,PHBFLTREN=0,PHAPOL=0,PHBPOL=0,QUADMODE=0,QUADIR=0,TOFDIR=0,QUADEN=0 */ FTM1_QDCTRL = 0x00U; /* FTM1_SWOCTRL: CH1OC=0,CH0OC=0 */ FTM1_SWOCTRL &= (uint32_t)~(uint32_t)( FTM_SWOCTRL_CH1OC_MASK | FTM_SWOCTRL_CH0OC_MASK ); /* FTM1_CONF: GTBEOUT=0,GTBEEN=0,BDMMODE=3,NUMTOF=0 */ FTM1_CONF = (uint32_t)((FTM1_CONF & (uint32_t)~(uint32_t)( FTM_CONF_GTBEOUT_MASK | FTM_CONF_GTBEEN_MASK | FTM_CONF_NUMTOF(0x1F) )) | (uint32_t)( FTM_CONF_BDMMODE(0x03) )); /* FTM1_PWMLOAD: LDOK=0,CH1SEL=0,CH0SEL=0 */ FTM1_PWMLOAD &= (uint32_t)~(uint32_t)( FTM_PWMLOAD_LDOK_MASK | FTM_PWMLOAD_CH1SEL_MASK | FTM_PWMLOAD_CH0SEL_MASK ); /* TM */ /* Set GPIOs for PWM outputs */ PORTA_BASE_PTR->PCR[ 8 ] = PORT_PCR_MUX( 3 ) | PORT_PCR_SRE_MASK | PORT_PCR_DSE_MASK; PORTA_BASE_PTR->PCR[ 9 ] = PORT_PCR_MUX( 3 ) | PORT_PCR_SRE_MASK | PORT_PCR_DSE_MASK; } |  |