| Код: -- Module Name: RISC_V_Core - Behavioral -- Project Name: RISC_V -- Target Devices: Efinix Trion T8F81 -- Tool versions: Efinity 2022.1 -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created 23/11/2022 -- Revision 0.1 - Initial version completed 9/12/2022 -- Revision 0.11 - Initial version tested 12/12/2022 -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -- -- entity RISC_V_Core is Port ( RST : in std_logic; -- Reset signal PORT_A_in : in std_logic_vector(7 downto 0); -- port declaration of bidirectional data line PORT_B_out : out std_logic_vector(7 downto 0); -- port declaration of bidirectional data line CLK : in std_logic -- Clock signal ); end RISC_V_Core; -- -- architecture Behavioral of RISC_V_Core is -- -- Enumerated operation type RISC_V_OPERATION is (o_SUM, o_SUB, o_SHIFT_LEFT, o_SHIFT_RIGHT, o_SRA, o_AND, o_OR, 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X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000", X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000", X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000", X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000", X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000", X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000" ); signal USER_MEM : RAM_MEM_2; signal XI : X_REG; -- This array is identical to XII and holds the GPRs signal XII : X_REG_1; -- This array is identical to XI and holds the GPRs signal DATA_FORMAT : DATA_F; -- Integer format for loading signal DATA_FORMAT_2 : DATA_F; -- Integer format for loading passed to Stage 4 signal PC : signed(31 downto 0) := to_signed(0,32); -- PC Register signal ARG1 : signed(31 downto 0) := to_signed(0,32); -- Argument 1 for operation signal ARG2 : signed(31 downto 0) := to_signed(0,32); -- Argument 2 for operation signal ARG3 : signed(31 downto 0) := to_signed(0,32); -- Argument 3 for operation signal SHIFT_STEPS : integer range 0 to 31 := 0; -- Shift Steps signal INSTRUCTION : std_logic_vector(31 downto 0) := X"00000000"; -- Instruction holding Register signal DESTINATION : std_logic_vector(4 downto 0) := "00000"; -- Instruction holding Register signal GPR : std_logic_vector(4 downto 0) := "00000"; -- General Purpose Register Index signal U_REG : std_logic_vector(31 downto 0) := X"00000000"; -- Formated U Type Immediate Register signal RS1 : std_logic_vector(4 downto 0) := "00000"; -- SR1 signal RS2 : std_logic_vector(4 downto 0) := "00000"; -- SR2 signal SR1_ST3 : std_logic_vector(4 downto 0) := "00000"; -- SR1 after Pipeline Stage 3 signal SR2_ST3 : std_logic_vector(4 downto 0) := "00000"; -- SR2 after Pipeline Stage 3 signal RES : signed(31 downto 0) := to_signed(0,32); -- Result after the instruction execution signal PORTA : signed(7 downto 0) := to_signed(0,8); -- PORT A buffer signal STAGE2_EN : std_logic := '0'; -- Enable bit for Stage 2 in the Pipeline signal STAGE3_EN : std_logic := '0'; -- Enable bit for Stage 3 in the Pipeline signal J_PP : std_logic := '0'; -- JALR post processing flag signal PC_WRITE : std_logic := '0'; -- PC write flag for Stage 4 signal MEM_STORE : std_logic := '0'; -- Register or Memory store flag for Stage 4 signal PC_WRITE_2 : std_logic := '0'; -- PC write flag for Stage 4 signal REG_STORE_2 : std_logic := '0'; -- Register or Memory store flag for Stage 4 signal LOAD_OP : std_logic := '0'; -- Load instrunction flag for post-processing signal sys_RES : std_logic := '0'; -- Sincronously asserted system Reset signal sinc_T1 : std_logic := '0'; -- Sinchronous Clock 1 signal sinc_T2 : std_logic := '0'; -- Sinchronous Clock 2 signal sinc_T3 : std_logic := '0'; -- Sinchronous Clock 3 signal RS1_REG : std_logic := '0'; -- Register flag for RS1 signal RS2_REG : std_logic := '0'; -- Register flag for RS2 signal RS1_REG_ST3 : std_logic := '0'; -- Register flag for RS1 in STAGE 3 signal RS2_REG_ST3 : std_logic := '0'; -- Register flag for RS1 in STAGE 3 signal OP_ADDRESS : signed(31 downto 0) := to_signed(0,32); -- LOAD ADDRESS -- function SIGN_EXTENDED_I(a: in STD_LOGIC_VECTOR ) return STD_LOGIC_VECTOR is begin if (a(31) = '1') then return( "111111111111111111111" & a(30 downto 20)); else return( "000000000000000000000" & a(30 downto 20)); end if; end function SIGN_EXTENDED_I; -- function SIGN_EXTENDED_J(a: in STD_LOGIC_VECTOR ) return STD_LOGIC_VECTOR is begin if (a(31) = '1') then return( "1111111111111" & a(19 downto 12)& a(20)& a(30 downto 21)); else return( "0000000000000" & a(19 downto 12)& a(20)& a(30 downto 21)); end if; end function SIGN_EXTENDED_J; -- function SIGN_EXTENDED_S(a: in STD_LOGIC_VECTOR ) return STD_LOGIC_VECTOR is begin if (a(31) = '1') then return( "111111111111111111111" & a(30 downto 25)&a(11 downto 7)); else return( "000000000000000000000" & a(30 downto 25)&a(11 downto 7)); end if; end function SIGN_EXTENDED_S; -- function SHIFTED_U(a: in STD_LOGIC_VECTOR ) return STD_LOGIC_VECTOR is begin return(a(31 downto 12) & "000000000000"); end function SHIFTED_U; -- function SIGN_EXTENDED_8(a: in SIGNED) return SIGNED is begin if (a(7) = '1') then return("1111111111111111111111111" & a(6 downto 0)); else return("0000000000000000000000000" & a(6 downto 0)); end if; end function SIGN_EXTENDED_8; -- function SIGN_EXTENDED_16(a: in SIGNED ) return SIGNED is begin if (a(15) = '1') then return("11111111111111111" & a(14 downto 0)); else return("00000000000000000" & a(14 downto 0)); end if; end function SIGN_EXTENDED_16; -- function ZERO_EXTENDED_8(a: in SIGNED ) return SIGNED is begin return("000000000000000000000000" & a(7 downto 0)); end function ZERO_EXTENDED_8; -- function ZERO_EXTENDED_16(a: in SIGNED ) return SIGNED is begin return("0000000000000000" & a(15 downto 0)); end function ZERO_EXTENDED_16; -- function SLT(a,b: in SIGNED ) return SIGNED is begin if a < b then return ("00000000000000000000000000000001"); else return("00000000000000000000000000000000"); end if; end function SLT; -- function SLTU(a,b: in SIGNED ) return SIGNED is begin if unsigned(a) < unsigned(b) then return ("00000000000000000000000000000001"); else return("00000000000000000000000000000000"); end if; end function SLTU; -- begin -- PORTA <= signed(PORT_A_in); -- Synchronous assertion and asynchronous de-assertion of the system Reset SYNC_RES: process (CLK, RST) begin if RST = '0' then sys_RES <= '0'; sinc_T1 <= '0'; sinc_T2 <= '0'; sinc_T3 <= '0'; else -- RST = '1' if rising_edge(CLK) then sinc_T1 <= '1'; sinc_T2 <= sinc_T1; sinc_T3 <= sinc_T2; -- System Reset when hardware reset is stable for 3 clocks if sinc_T1 = '1' AND sinc_T2 = '1' AND sinc_T3 = '1' then sys_RES <= '1'; end if; end if; end if; -- RST end process SYNC_RES; -- -- --============================== PIPELINE STAGE 1 =================================== --================================== ENCODING ======================================= -- Stage_1: process (CLK, sys_RES) begin if sys_RES = '0' then STAGE2_EN <= '0'; RS1_REG <= '0'; RS2_REG <= '0'; PC <= X"0000_0000"; else -- sys_RES = '1' if rising_edge(CLK) then if (PC_WRITE='0') then PC <= PC + 1; -- Increases the Program Counter else PC <= RES(31 downto 1) & '0'; -- Updates the PC from Pipeline Stage 2 end if; -- PC_WRITE STAGE2_EN <= '1'; -- Enable the Pipeline Stage 2 DESTINATION <= PROG_MEM(to_integer(PC))(11 downto 7); -- Reading the instruction if PROG_MEM(to_integer(PC))(19 downto 15)="00000" then ARG1 <= (others => '0'); else ARG1 <= XI(to_integer(unsigned(PROG_MEM(to_integer(PC))(19 downto 15)))); end if; if PROG_MEM(to_integer(PC))(24 downto 20)="00000" then ARG2 <= (others => '0'); else ARG2 <= XII(to_integer(unsigned(PROG_MEM(to_integer(PC))(24 downto 20)))); end if; RS1 <= PROG_MEM(to_integer(PC))(19 downto 15); -- Source Register 1 is passed to Pipeline Stage 2 RS2 <= PROG_MEM(to_integer(PC))(24 downto 20); -- Source Register 2 is passed to Pipeline Stage 2 RS1_REG <= '1'; -- ARG1 (Argument 1) is a register unless otherwise stated in the SM below RS2_REG <= '1'; -- ARG2 (Argument 2) is a register unless otherwise stated in the SM below ARG3 <= signed (sign_extended_S(PROG_MEM(to_integer(PC)))) + XI(to_integer(unsigned(PROG_MEM(to_integer(PC))(19 downto 15)))); case PROG_MEM(to_integer(PC))(6 downto 2) is -- Encoding the operand when "00000" => ---------------------------------------- LOAD opcode ARG3 <= signed(sign_extended_I(PROG_MEM(to_integer(PC)))); OPERATION <= o_LOAD; case PROG_MEM(to_integer(PC))(14 downto 12) is -- Encoding func.3 when "001" => ------------------------ LH DATA_FORMAT <= l_16; when "010" => ------------------------ LW DATA_FORMAT <= l_32; when "100" => ------------------------ LBU DATA_FORMAT <= l_8_U; when "101" => ------------------------ LHU DATA_FORMAT <= l_16_U; when others => ------------------------ LB ("000") DATA_FORMAT <= l_8; end case; when "00011" => --------------------------------------- MISC_MEM opcode case PROG_MEM(to_integer(PC))(14 downto 12) is -- Encoding func.3 when "001" => ------------------------ FENCEI when others => ------------------------ FENCE ("000") end case; when "00100" => --------------------------------------- OP-IMM opcode ARG2 <= signed(sign_extended_I(PROG_MEM(to_integer(PC)))); RS2_REG <= '0'; -- ARG2 is not a GPR case PROG_MEM(to_integer(PC))(14 downto 12) is -- Encoding func.3 when "001" => ------------------------ SLLI OPERATION <= o_SHIFT_LEFT; when "010" => ------------------------ SLTI OPERATION <= o_SLT; when "011" => ------------------------ SLTIU OPERATION <= o_SLTU; when "100" => ------------------------ XORI OPERATION <= o_XOR; when "101" => case PROG_MEM(to_integer(PC))(30) is -- Encoding func.7 when '1' => ------------------------ SRAI; --OPERATION <= o_SRA; when others => ------------------------ SRLI; ('0') OPERATION <= o_SHIFT_RIGHT; end case; when "110" => ------------------------ ORI OPERATION <= o_OR; when "111" => ------------------------ ANDI OPERATION <= o_AND; when others => ------------------------ ADDI ("000") OPERATION <= o_SUM; end case; when "00101" => ------------------------ AUIPC / OPCODE OPERATION <= o_SUM; ARG1 <= signed(shifted_U(PROG_MEM(to_integer(PC)))); RS1_REG <= '0'; -- ARG1 is Immediate ARG2 <= PC; RS2_REG <= '0'; -- ARG2 is not a GPR when "01000" => --------------------------------------- STORE opcode OPERATION <= o_SAVE; case PROG_MEM(to_integer(PC))(14 downto 12) is when "000" => ------------------------ SB DATA_FORMAT <= l_8_U; when "001" => ------------------------ SH DATA_FORMAT <= l_16_U; when others => ------------------------ SW ("010") DATA_FORMAT <= l_32; end case; when "01100" => --------------------------------------- OP opcode case PROG_MEM(to_integer(PC))(14 downto 12) is -- Encoding func.3 when "000" => case PROG_MEM(to_integer(PC))(30) is -- Encoding func.7 when '1' => ------------------------ SUB OPERATION <= o_SUB; when others => ------------------------ ADD ('0') OPERATION <= o_SUM; end case; when "001" => ------------------------ SLL OPERATION <= o_SHIFT_LEFT; when "010" => ------------------------ SLT OPERATION <= o_SLT; when "011" => ------------------------ SLTU OPERATION <= o_SLTU; when "100" => ------------------------ XOR OPERATION <= o_XOR; when "101" => case PROG_MEM(to_integer(PC))(30) is -- Encoding func.7 when '1' => ------------------------ SRA -- OPERATION <= o_SRA; when others => ------------------------ SRL ('0') OPERATION <= o_SHIFT_RIGHT; end case; when "110" => ------------------------ OR OPERATION <= o_OR; when others => ------------------------ AND ("111") OPERATION <= o_AND; end case; when "01101" => ------------------------ LUI / OPCODE ARG1 <= signed(shifted_U(PROG_MEM(to_integer(PC)))); RS1_REG <= '0'; -- ARG1 is Immediate ARG2 <= (others => '0'); RS2_REG <= '0'; -- ARG2 is not a GPR OPERATION <= o_SUM; when "11000" => ---------------------------------------- BRANCH opcode case PROG_MEM(to_integer(PC))(14 downto 12) is -- Encoding func.3 when "001" => ------------------------ BNE OPERATION <= o_BNE; when "100" => ------------------------ BLT OPERATION <= o_BLT; when "101" => ------------------------ BGE OPERATION <= o_BGE; when "110" => ------------------------ BLTU OPERATION <= o_BLTU; when "111" => ------------------------ BGEU OPERATION <= o_BGEU; when others => ------------------------ BEQ ("000") OPERATION <= o_BEQ; end case; when "11001" => ------------------------ JALR / OPCODE ARG2 <= signed(sign_extended_I(PROG_MEM(to_integer(PC)))); RS2_REG <= '0'; -- ARG2 is not a GPR OPERATION <= o_SUM; when "11011" => ------------------------ JAL / OPCODE ARG1 <= signed (sign_extended_J(PROG_MEM(to_integer(PC)))); RS1_REG <= '0'; -- ARG1 is Immediate ARG2 <= PC; RS2_REG <= '0'; -- ARG2 is not a GPR OPERATION <= o_SUM; when "11100" => ---------------------------------------- SYSTEM opcode case PROG_MEM(to_integer(PC))(14 downto 12) is -- Encoding func.3 when "000" => case PROG_MEM(to_integer(PC))(25)is -- Encoding func.7 when '0' => ------------------------ ECALL when '1' => ------------------------ EBREAK when others => NULL; end case; when "001" => ------------------------ CSRRW when "010" => ------------------------ CSRRS when "011" => ------------------------ CSRRC when "101" => ------------------------ CSRRWI when "110" => ------------------------ CSRRSI when "111" => ------------------------ CSRRCI when others => NULL; end case; when others => NULL; end case; -- end if; -- rising edge (CLK) end if; -- sys_RES end process Stage_1; -- -- -- --============================== PIPELINE STAGE 2 =================================== --================================= EXECUTING ======================================= -- Stage_2: process (CLK, sys_RES, STAGE2_EN) begin if sys_RES = '0' then STAGE3_EN <= '0'; RS1_REG_ST3 <= '0'; RS2_REG_ST3 <= '0'; else -- sys_RES = '1' if rising_edge(CLK) and (STAGE2_EN='1') then STAGE3_EN <= '1'; -- Enables the Stage 3 of the pipeline GPR <= DESTINATION; -- Passes the GPR index from Stage 1 to Stage 3 RS1_REG_ST3 <= RS1_REG; RS2_REG_ST3 <= RS2_REG; DATA_FORMAT_2 <= DATA_FORMAT; -- Passes the Load format from Stage 1 to Stage 3 MEM_STORE <= '0'; -- the instruction result is stored in a GPR by default LOAD_OP <= '0'; -- no Load Operation flag by default PC_WRITE <= '0'; -- no modifying of the PC register by default -- if the result of the previous operation is going to be stored into the same register as ARG1 then it -- is used instead as an input of the operation if ((GPR = RS1) and (RS1_REG = '1') and (RS1_REG_ST3 = '1')) then case OPERATION is when o_SUM => RES(31 downto 0) <= RES + ARG2; when o_SUB => RES(31 downto 0) <= RES - ARG2; when o_SHIFT_LEFT => RES(31 downto 0) <= shift_left(RES, to_integer(ARG2(4 downto 0))); when o_SHIFT_RIGHT => RES(31 downto 0) <= shift_right(RES, to_integer(ARG2(4 downto 0))); -- when o_SRA => RES(31 downto 0) <= RES sra to_integer(ARG2(4 downto 0)); when o_AND => RES(31 downto 0) <= RES and ARG2; when o_OR => RES(31 downto 0) <= RES or ARG2; when o_XOR => RES(31 downto 0) <= RES xor ARG2; when o_SLT => RES(31 downto 0) <= SLT(RES, ARG2); when o_SLTU => RES(31 downto 0) <= SLTU(RES, ARG2); when o_LOAD => if (ARG3) = 0 then RES <= ZERO_EXTENDED_8(PORTA); else RES <= signed(USER_MEM(to_integer(ARG3))); end if; LOAD_OP <= '1'; -- sets the Load Operation flag for Stage 3 when o_SAVE => MEM_STORE <= '1'; -- result is stored in the user RAM memory OP_ADDRESS <= RES + ARG3; case DATA_FORMAT is when l_16_U => RES <= ZERO_EXTENDED_16(ARG2); when l_8_U => RES <= ZERO_EXTENDED_8(ARG2); when others => RES <= ARG2; -- l_32 end case; when o_BEQ => if RES = ARG2 then RES <= ARG3; PC_WRITE <= '1'; end if; when o_BNE => if RES /= ARG2 then RES <= ARG3; PC_WRITE <= '1'; end if; when o_BLT => if RES < ARG2 then RES <= ARG3; PC_WRITE <= '1'; end if; when o_BGE => if RES > ARG2 then RES <= ARG3; PC_WRITE <= '1'; end if; when o_BLTU => if unsigned(RES) < unsigned(ARG2) then RES <= ARG3; PC_WRITE <= '1'; end if; when o_BGEU => if unsigned(RES) > unsigned(ARG2) then RES <= ARG3; PC_WRITE <= '1'; end if; when others => NULL; end case; -- if the result of the previous operation is going to be stored into the same register as ARG2 then it -- is used instead as an input of the operation elsif ((GPR = RS2) and (RS2_REG = '1') and (RS2_REG_ST3 = '1')) then case OPERATION is when o_SUM => RES(31 downto 0) <= ARG1 + RES; when o_SUB => RES(31 downto 0) <= ARG1 - RES; when o_SHIFT_LEFT => RES(31 downto 0) <= shift_left(ARG1, to_integer(RES(4 downto 0))); when o_SHIFT_RIGHT => RES(31 downto 0) <= shift_right(ARG1, to_integer(RES(4 downto 0))); -- when o_SRA => RES(31 downto 0) <= ARG1 sra to_integer(RES(4 downto 0)); when o_AND => RES(31 downto 0) <= ARG1 and RES; when o_OR => RES(31 downto 0) <= ARG1 or RES; when o_XOR => RES(31 downto 0) <= ARG1 xor RES; when o_SLT => RES(31 downto 0) <= SLT(ARG1, RES); when o_SLTU => RES(31 downto 0) <= SLTU(ARG1, RES); when o_LOAD => if (ARG3) = 0 then RES <= ZERO_EXTENDED_8(PORTA); else RES <= signed(USER_MEM(to_integer(ARG3))); end if; LOAD_OP <= '1'; -- sets the Load Operation flag for Stage 3 when o_SAVE => MEM_STORE <= '1'; -- result is stored in the user RAM memory OP_ADDRESS <= ARG1 + ARG3; case DATA_FORMAT is when l_16_U => RES <= ZERO_EXTENDED_16(ARG2); when l_8_U => RES <= ZERO_EXTENDED_8(ARG2); when others => RES <= ARG2; -- l_32 end case; when o_BEQ => if ARG1 = RES then RES <= ARG3; PC_WRITE <= '1'; end if; when o_BNE => if ARG1 /= RES then RES <= ARG3; PC_WRITE <= '1'; end if; when o_BLT => if ARG1 < RES then RES <= ARG3; PC_WRITE <= '1'; end if; when o_BGE => if ARG1 > RES then RES <= ARG3; PC_WRITE <= '1'; end if; when o_BLTU => if unsigned(ARG1) < unsigned(RES) then RES <= ARG3; PC_WRITE <= '1'; end if; when o_BGEU => if unsigned(ARG1) > unsigned(RES) then RES <= ARG3; PC_WRITE <= '1'; end if; when others => NULL; end case; else case OPERATION is when o_SUM => RES(31 downto 0) <= ARG1 + ARG2; when o_SUB => RES(31 downto 0) <= ARG1 - ARG2; when o_SHIFT_LEFT => RES(31 downto 0) <= shift_left(ARG1, to_integer(ARG2(4 downto 0))); when o_SHIFT_RIGHT => RES(31 downto 0) <= shift_right(ARG1, to_integer(ARG2(4 downto 0))); -- when o_SRA => RES(31 downto 0) <= ARG1 sra to_integer(ARG2(4 downto 0)); when o_AND => RES(31 downto 0) <= ARG1 and ARG2; when o_OR => RES(31 downto 0) <= ARG1 or ARG2; when o_XOR => RES(31 downto 0) <= ARG1 xor ARG2; when o_SLT => RES(31 downto 0) <= SLT(ARG1, ARG2); when o_SLTU => RES(31 downto 0) <= SLTU(ARG1, ARG2); when o_LOAD => if (ARG3) = 0 then RES <= ZERO_EXTENDED_8(PORTA); else RES <= signed(USER_MEM(to_integer(ARG3))); end if; LOAD_OP <= '1'; -- sets the Load Operation flag for Stage 3 when o_SAVE => MEM_STORE <= '1'; -- result is stored in the user RAM memory OP_ADDRESS <= ARG1 + ARG3; case DATA_FORMAT is when l_16_U => RES <= ZERO_EXTENDED_16(ARG2); when l_8_U => RES <= ZERO_EXTENDED_8(ARG2); when others => RES <= ARG2; -- l_32 end case; when o_BEQ => if ARG1 = ARG2 then RES <= ARG3; PC_WRITE <= '1'; end if; when o_BNE => if ARG1 /= ARG2 then RES <= ARG3; PC_WRITE <= '1'; end if; when o_BLT => if ARG1 < ARG2 then RES <= ARG3; PC_WRITE <= '1'; end if; when o_BGE => if ARG1 > ARG2 then RES <= ARG3; PC_WRITE <= '1'; end if; when o_BLTU => if unsigned(ARG1) < unsigned(ARG2) then RES <= ARG3; PC_WRITE <= '1'; end if; when o_BGEU => if unsigned(ARG1) > unsigned(ARG2) then RES <= ARG3; PC_WRITE <= '1'; end if; when others => NULL; end case; end if; end if; -- rising edge (CLK) end if; -- sys_RES end process Stage_2; -- -- -- --============================== PIPELINE STAGE 3 =================================== --=================================== SAVING ======================================== Stage_3: process (CLK, sys_RES, STAGE3_EN) begin if sys_RES = '0' then NULL; else if rising_edge(CLK) and STAGE3_EN = '1' then if (MEM_STORE = '0') then -- Result is stored in GPR if LOAD_OP = '0' then if J_PP = '0' then XI(to_integer(unsigned(GPR))) <= RES; XII(to_integer(unsigned(GPR))) <= RES; else XI(to_integer(unsigned(GPR))) <= RES(31 downto 1) & '0'; XII(to_integer(unsigned(GPR))) <= RES(31 downto 1) & '0'; end if; else case DATA_FORMAT_2 is when l_32 => XI(to_integer(unsigned(GPR))) <= RES; XII(to_integer(unsigned(GPR))) <= RES; when l_16 => XI(to_integer(unsigned(GPR))) <= SIGN_EXTENDED_16(RES); XII(to_integer(unsigned(GPR))) <= SIGN_EXTENDED_16(RES); when l_8 => XI(to_integer(unsigned(GPR))) <= SIGN_EXTENDED_8(RES); XII(to_integer(unsigned(GPR))) <= SIGN_EXTENDED_8(RES); when l_16_U => XI(to_integer(unsigned(GPR))) <= ZERO_EXTENDED_16(RES); XII(to_integer(unsigned(GPR))) <= ZERO_EXTENDED_16(RES); when l_8_U => XI(to_integer(unsigned(GPR))) <= ZERO_EXTENDED_8(RES); XII(to_integer(unsigned(GPR))) <= ZERO_EXTENDED_8(RES); when others => NULL; end case; end if; --LOAD_OP else -- Result is stored in user RAM if OP_ADDRESS = 0 then -- PORT B is an 8 bit output only and is memory mapped at address 0 (User RAM) PORT_B_out <= std_logic_vector(RES(7 downto 0)); else USER_MEM(to_integer(unsigned(OP_ADDRESS))) <= std_logic_vector(RES); end if; end if; -- MEM_STORE end if; -- rising edge (CLK) end if; -- sys_RES end process Stage_3; -- -- -- -- end Behavioral; | |