#if defined(RUN_AT_48MHZ)
   // Setup for Fcy=48MHz for core and Fpb=48MHz for peripheral
   // Explorer 16 board has 8.000MHz crystal, FPLLIDIV=DIV_4 divide this
   // 8.000MHz by 2, FPLLMUL=MUL_24 multiply 2.000MHz by 24 and result is 48MHz
   // for core. FPBDIV=DIV_1 divide core clock by 1 and result is 48MHz clock for
   // peripheral
   #pragma config POSCMOD=XT, FNOSC=PRIPLL
   #pragma config FPLLIDIV=DIV_4, FPLLMUL=MUL_24, FPLLODIV=DIV_1
   #pragma config FPBDIV=DIV_1, FWDTEN=OFF, CP=OFF, BWP=OFF
#elif defined(RUN_AT_56MHZ)
   // Setup for Fcy=56MHz for core and Fpb=56MHz for peripheral
   // Explorer 16 board has 8.000MHz crystal, FPLLIDIV=DIV_3 divide this
   // 8.000MHz by 3, FPLLMUL=MUL_21 multiply 2.6666MHz by 21 and result is 56MHz
   // for core. FPBDIV=DIV_1 divide core clock by 1 and result is 56MHz clock for
   // peripheral
   #pragma config POSCMOD=XT, FNOSC=PRIPLL
   #pragma config FPLLIDIV=DIV_3, FPLLMUL=MUL_21, FPLLODIV=DIV_1
   #pragma config FPBDIV=DIV_1, FWDTEN=OFF, CP=OFF, BWP=OFF

#elif defined(RUN_AT_64MHZ)
   // Setup for Fcy=64MHz for core and Fpb=32MHz for peripheral
   // Explorer 16 board has 8.000MHz crystal, FPLLIDIV=DIV_2 divide this
   // 8.000MHz by 2, FPLLMUL=MUL_16 multiply 4.000MHz by 16 and result is 64MHz
   // for core. FPBDIV=DIV_2 divide core clock by 2 and result is 32MHz clock for
   // peripheral
   #pragma config POSCMOD=XT, FNOSC=PRIPLL
   #pragma config FPLLIDIV=DIV_2, FPLLMUL=MUL_16, FPLLODIV=DIV_1
   #pragma config FPBDIV=DIV_2, FWDTEN=OFF, CP=OFF, BWP=OFF

#elif defined(RUN_AT_72MHZ)
   // Setup for Fcy=72MHz for core and Fpb=36MHz for peripheral
   // Explorer 16 board has 8.000MHz crystal, FPLLIDIV=DIV_2 divide this
   // 8.000MHz by 2, FPLLMUL=MUL_18 multiply 4.000MHz by 18 and result is 72MHz
   // for core. FPBDIV=DIV_2 divide core clock by 2 and result is 36MHz clock for
   // peripheral
   #pragma config POSCMOD=XT, FNOSC=PRIPLL
   #pragma config FPLLIDIV=DIV_2, FPLLMUL=MUL_18, FPLLODIV=DIV_1
   #pragma config FPBDIV=DIV_2, FWDTEN=OFF, CP=OFF, BWP=OFF

#elif defined(RUN_AT_80MHZ)
   // Setup for Fcy=80MHz for core and Fpb=40MHz for peripheral
   // Explorer 16 board has 8.000MHz crystal, FPLLIDIV=DIV_2 divide this
   // 8.000MHz by 2, FPLLMUL=MUL_20 multiply 4.000MHz by 18 and result is 80MHz
   // for core. FPBDIV=DIV_2 divide core clock by 2 and result is 40MHz clock for
   // peripheral
   #pragma config POSCMOD=XT, FNOSC=PRIPLL
   #pragma config FPLLIDIV=DIV_2, FPLLMUL=MUL_20, FPLLODIV=DIV_1
   #pragma config FPBDIV=DIV_2, FWDTEN=OFF, CP=OFF, BWP=OFF

#else
#error "Wrong defined PIC32 RUN_AT_xxMHZ frequency, please see HardwareProfile.h ."
#endif

typedef struct tagSYSPBCLK{
   uint32   fsys_clk;   // System clock set by pragma directive ( fuses sys clk )
   uint32   fpb_clk;   // Peripheral clock set by pragma directive ( fuses pb clk )
   uint32   sys_clk;   // System clock set by OSCCON register
   uint32   pb_clk;      // Peripheral clock set by OSCCON register
}SYSPBCLK;   

/*
   GetSysAndPbClk() is useful function to check if system and
   peripheral clock are initialized properly. It use as input
   parameter desired system frequency and return as
   result a structure from type SYSPBCLK filled with actual
   system and peripheral clock. SYSPBCLK has two identical
   sections, one set from pragma directive, and second
   contain actual frequency read from OSCCON register.

   This funcion can be used in debug process. Let say we have
   8MHz crystal and we want to have 64MHz system clock and 32MHz
   peripheral clock. GetSysAndPbClk() will help us to see
   if FPLLIDIV, FPLLMUL, FPLLODIV and FPBDIV have right values.
*/
uint8 const pllidiv_array[8]    = {1, 2, 3, 4, 5, 6,10,12};
uint8 const pllmul_array[8]      = {15,16,17,18,19,20,21,24};
uint16 const pllodiv_array[8]    = {1, 2, 4, 8,16,32,64,256};
uint8 const pbdiv_array[4]       = {1, 2, 4, 8};

void GetSysAndPbClk(uint32 crystal, // input quartz crystal, Hz
               SYSPBCLK *result)
{         
uint32   fpllidiv,   // PLL input divider
      fpllmult,   // PLL multiplier
      fpllodiv,   // PLL output divider
      fpbdiv,      // Peripheral Bus Clock Divider
      pllmult,   // PLL multiplier
      pllodiv,   // PLL output divider
      pbdiv;      // Peripheral Bus Clock Divider
      
   // Oscillator configuration from #pragmas
   fpllidiv    =    pllidiv_array[DEVCFG2bits.FPLLIDIV];
   fpllmult    =    pllmul_array[DEVCFG2bits.FPLLMUL];
   fpllodiv   =    pllodiv_array[DEVCFG2bits.FPLLODIV];      
   fpbdiv       =    pbdiv_array[DEVCFG1bits.FPBDIV];
   // Oscillator configurations from OSCCON register
   pllmult    =    pllmul_array[OSCCONbits.PLLMULT];
   pllodiv    =    pllodiv_array[OSCCONbits.PLLODIV];
   pbdiv       =    pbdiv_array[OSCCONbits.PBDIV];   
   
   // Calculate system clock and peripheral bus clock
   // set by pragma directive
   result->fsys_clk    =   ( crystal * fpllmult ) / ( fpllidiv * fpllodiv );
   result->fpb_clk      =   result->fsys_clk / fpbdiv;
   
   // Calculate system clock and peripheral bus clock
   // set by OSCCON register
   result->sys_clk      =   ( crystal * pllmult ) / ( fpllidiv * pllodiv );
   result->pb_clk      =   result->sys_clk / pbdiv;
}

   // Setup for Fcy=80MHz for core and Fpb=40MHz for peripheral
   // Explorer 16 board has 8.000MHz crystal, FPLLIDIV=DIV_2 divide this
   // 8.000MHz by 2, FPLLMUL=MUL_20 multiply 4.000MHz by 18 and result is 80MHz
   // for core. FPBDIV=DIV_2 divide core clock by 2 and result is 40MHz clock for
   // peripheral
   #pragma config POSCMOD=XT, FNOSC=PRIPLL
   #pragma config FPLLIDIV=DIV_2, FPLLMUL=MUL_20, FPLLODIV=DIV_1
   #pragma config FPBDIV=DIV_2, FWDTEN=OFF, CP=OFF, BWP=OFF