Разни процесори разни edge sensitive входове,
май повечето дето съм виждал просто гледат за разлика между две съседни стойности
на нацъканото навътре ниво, с тях няма да стане.

To ensure the NVIC detects the interrupt, the peripheral must assert the interrupt signal for
at least one clock cycle, during which the NVIC detects the pulse and latches the interrupt.

The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described
as edge-triggered interrupts.
A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically
this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. A
pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor
clock. To ensure the NVIC detects the interrupt, the peripheral must assert the interrupt signal for
at least one clock cycle, during which the NVIC detects the pulse and latches the interrupt.
When the processor enters the ISR, it automatically removes the pending state from the interrupt
(see “Hardware and Software Control of Interrupts” on page 122 for more information). For a
level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR,
the interrupt becomes pending again, and the processor must execute its ISR again. As a result,
the peripheral can hold the interrupt signal asserted until it no longer needs servicing.