void Xclock(bool en) {
    if (en) {
        // Enable the GPIOB clock
        RCC->AHB2ENR |= RCC_AHB2ENR_GPIOBEN;

        // Set PB6 to Alternate Function mode for MCO output
        GPIOB->MODER &= ~GPIO_MODER_MODE6;       // Clear mode bits for PB6
        GPIOB->MODER |= GPIO_MODER_MODE6_1;      // Set PB6 to Alternate Function mode

        // Ensure the MCO alternate function is selected (AF0)
        GPIOB->AFR[0] &= ~GPIO_AFRL_AFSEL6;      // Clear AF bits for PB6, AF0 is required for MCO

        // Clear any previous MCO configuration
        RCC->CFGR &= ~(RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE);

        // Set MCO source to SYSCLK and configure the prescaler to divide by 2
        RCC->CFGR |= (0b11 << RCC_CFGR_MCOSEL_Pos);  // MCO source = SYSCLK (0b11 for SYSCLK)
        RCC->CFGR |= RCC_CFGR_MCOPRE_DIV2;           // Set MCO prescaler to 2 (66 MHz / 2 = 33 MHz)
    } else {
        // Disable the MCO output by setting PB6 to its default input mode
        GPIOB->MODER &= ~GPIO_MODER_MODE6;       // Set PB6 to input mode
    }
}


void configureSystemClock(void) {
    // Enable HSE (High-Speed External) clock
    RCC->CR |= RCC_CR_HSEON;
    while (!(RCC->CR & RCC_CR_HSERDY));  // Wait until HSE is ready

    // Configure PLL to multiply 12 MHz HSE to 66 MHz
    RCC->PLLCFGR = RCC_PLLCFGR_PLLSRC_HSE   // Select HSE as PLL source
                 | (1 << RCC_PLLCFGR_PLLM_Pos)   // PLLM = 1
                 | (22 << RCC_PLLCFGR_PLLN_Pos)  // PLLN = 22 (12 MHz * 22 = 264 MHz VCO)
                 | (4 << RCC_PLLCFGR_PLLR_Pos);  // PLLR = 4 (264 MHz / 4 = 66 MHz)

    // Enable the PLL
    RCC->CR |= RCC_CR_PLLON;
    while (!(RCC->CR & RCC_CR_PLLRDY));  // Wait until PLL is ready

    // Select PLL as the system clock source
    RCC->CFGR |= RCC_CFGR_SW_PLL;
    while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL); // Wait until PLL is the system clock
}


void setup(void) {
    configureSystemClock();
    Xclock(true);
}


void loop(void) {
}

const uint8_t  AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};

void Xclock(bool en) {
    if (en) {
        // Enable the GPIOA clock
        RCC->AHB2ENR |= (1U<<0);

        // Set PA8 to Alternate Function mode for MCO output
        GPIOA->MODER |= (1U<<17);       
        GPIOA->MODER &= ~(1U<<16);   

        // Ensure the MCO alternate function is selected (AF0)
        GPIOA->AFR[1] &= ~(1U<<0);     
        GPIOA->AFR[1] &= ~(1U<<1);     
        GPIOA->AFR[1] &= ~(1U<<2);     
        GPIOA->AFR[1] &= ~(1U<<3);     

        // Clear any previous MCO configuration
        RCC->CFGR &= ~(RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE);

        // Set MCO source to SYSCLK and configure the prescaler to divide by 2
        RCC->CFGR |= (0b11 << RCC_CFGR_MCOSEL_Pos);  // MCO source = SYSCLK (0b11 for SYSCLK)
        RCC->CFGR |= RCC_CFGR_MCOPRE_DIV2;           // Set MCO prescaler to 2 (66 MHz / 2 = 33 MHz)
    } else {
        // Disable the MCO output by setting PA8 to its default input mode       
        GPIOA->MODER &= ~ (1U<<17);       
        GPIOA->MODER &= ~(1U<<16); 
    }
}